The present invention relates to methods for removing circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool.
It is a difficult task to verify that a system design, under the influence of simultaneous switching noise (SSN), meets a required noise margin. Existing simulation techniques can be used to predict the magnitude of a noise event caused by a given set of aggressor signals on a victim pin, but these techniques do not address how to determine the set of aggressors or how to interpret the resulting noise. The naïve approach of assuming all possible pins are aggressors, and that any noise spikes that cross into the switching region of an input buffer is a failure, presents too many false failures.
Examples of where the naïve approach predicts failures, when none are seen in practice, are PCI (Peripheral Component Interconnect) and DDR (Double data rate) buses. Both of these buses incorporate high drive strength output buffers which are capable of inducing significant amounts of SSN voltage noise. These buses function properly because aggressors and victims are synchronously aligned. This alignment guarantees that the noise event occurs when the bus signals are switching and the receiver is not sampling. Under this condition, a violation of the input threshold, due to noise, is not a real failure.
It is in this context that embodiments of the invention arise.